Hi,

Please check out the job description below

Key Responsibilities: 
The Physical Design engineer will be responsible for the planning and execution of all SoC or IP physical design activities for Client’s next generation products. She/he will be responsible for execution of Physical Design (place and route) duties both at block level, IP/macro level, as well as chip-level. This includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Logical vs. Schematic (LVS) checks. 

The candidate will: 
• Provide technical direction, mentoring, skill development 
• Be a forward thinker to improve process and innovation 
• Interface with other local and global front end and Physical Design Managers/Directors to define schedules, resource requirements etc., 
• Provide leadership and direction in crisis 
• Interface with front-end ASIC teams to resolve issues and problems 
• Responsible for execution of program. Multiple projects on the go. 

In addition, strong communication skills and an ability to work in large groups are essential to being successful. Insight into multi-site project development will be an asset. 
The following aspects are desirable: 
• Technical 
o Understanding Verilog HDL 
o Understanding Deep Submicron effects such as 90nm and below 
o Understanding OCV, DFM, DFY 
o Excellent Block level and Full-chip physical design skills 
o Back ground of all aspects of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc 
o Hands on recent or past experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools 
o Understanding of complete SoC development cycle, from architecture to post-silicon debug preferred 
o Should have participated in a minimum of 3 fullchip tapeouts 
• Management 
o Minimum 3 years of ASIC physical design management experience, working with global teams 
o Self-motivated, conflict resolution skills, and experience working with global teams across time zones 
o Detail oriented and schedule driven 
o People management skills as well as technical project management skills

Please check out the following and refer to any of your friends who are eligible for a top company in semiconductor industry.

Best Regards,  

Sathya

| Talent Acquisition Specialist |  SigmaEdge| Office: +91 40 4067 4441. Extn.211 | Mobile: +91 955 0828 363 | Fax: +91 404 067 4445  |Mail Id: satya@sigmaedge.com|

| SigmaEdge Software Consulting (P) Ltd | 9-1-127/3, 43, S D Road, Secunderabad - 500 003 | Website: www.sigmaedge.com |