The responsibility of this position is to support ASIC from RTL to silicon with focus into areas related to synthesis, formal verification, timing, DFT/test.

The incumbent should be proficient in any of the following areas - RTL coding linting/checking, logical synthesis, formal verification, power optimization, timing assertion creation and validation, clock tree implementation, optimization of floorplan, placement and routing, STA, DFT plan, implementation, validation and silicon debugging

Qualification

• Proficiency in scripting with Tcl/Perl and automation of design process.
• Knowledgeable of libraries (.lib, CCS), logic design, DFT, constraints and STA
• Familiar or experienced with Verilog, synthesis flow and tool DC, formal verification and tools Conformal ASIC or Formality
• Should have strong hands-on experience of PT/ET, HyperScale, skills and techniques of variation handling and statistical timing analysis