Scope of Responsibility/Expectations

Work closely with other members of a small, focused, team with responsibility for designing both the pads and the control circuitry associated with a DDR interface. Design at the transistor level circuitry in the control block sitting between the DDR pads and the standard memory signals going to and from the array. This control block decodes the instructions from the bus, lines up input and output signals with the high frequency clock using DLLs or PLLs, and converts input signals to array commands and takes array output signals, such as, data, and sends them to the pads following the DDR standard protocol. Work under the supervision of a senior
project leader. Design, simulate, and supervise layout of blocks of circuitry. Work with product and test engineers evaluating and debugging circuit performance after silicon processing.

Specific Required Knowledge

• Circuit theory • Impact of layout parasitic capacitance

• PLL/DLL design techniques and resistance on signal integrity, speed,

• Probability and statistics and power dissipation, along with layout

• Logic design techniques to minimize these effects

Useful Skills

• Transistor level simulation • Physical design, i. e., layout

• Parasitic extraction • Logic verification

• Critical path modeling • Mixed-mode Verilog

Education and Experience

Masters or equivalent in Electrical Engineering, Physics, Computer Science, or related fields. A
track record of placing memory chips into production is required. Experience designing DDR
pads that meet JEDEC electrical specifications and that have industry standard ESD tolerance is
desired. Experience with DRAMs or with DRAM Controller s and PHYs is applicable.
Demonstration of innovation and leading-edge expertise through publications and patents is
desired.