Levels – Engineers / MTS / SMTS

Exp: - 3-10 Years

• OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions
• Strong Familiarity with Verification Methodologies such as OVM, AVM, or VMM
• Familiarity with Verilog and General Logic Design concepts
• Knowledge of system-level / x86 architecture
• Experience in verifying complex designs.
• Experience with processor verification and SOC Debug architectures is a plus
• Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
• BS/MS EE, CE, or CS

Mail Resume to: dchetan@onssearch.in

Contact no :  +91-9886102429