Timing Closure / STA - Lead Engineer - 6-8 yrs. - Established Start up. (closed)
ASIC/SoC design & implementation experience with specific background in the areas of synthesis, static timing analysis, and timing closure techniques. Seeking highly motivated, energetic, team-oriented “Timing Closure/STA Lead” willing to take the challenge of delivering the first pass success of complex SoCs with 0 ppm target using the latest timing signoff techniques
Includes definition and development of signoff methodology and corresponding implementation solution and flow for STA, Crosstalk Delay and Noise analysis for digital ASIC/SoCs.
Full chip timing constraints development, full chip Static Timing Analysis and Signoff for a complex, multi-clock, multi-voltage SoC. Streamlining the timing signoff criterions, timing analysis methodologies and flows.
Analyze and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow
The STA Lead would be working with experienced and motivated team of Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address the design challenges in the context of the block, chip, and overall system.
Self starter with 6-8 years of experience on SOC/Chip level Timing closure and Signoff of high speed complex design with multiple clocks and power domains with minimal supervision.
Expertise in developing and owning full chip Timing Constraints for a complex, multi-clock, multi-voltage SoCs
Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...)
Good understanding of deep submicron parasitic effects, crosstalk effects, newer statistical timing approaches
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