Staff Engineers / Architect - ASIC Verification (Networking/Storage) - 6yrs - 10yrs. (closed)
POSITIONS = STAFF ENGINEERS / ARCHITECT
Duties & responsibilities:
¢ Engineer will be responsible for aspects of ASIC development with a specific focus on verification.
¢ Engineer will implement verification infrastructure including stimulus, checking and monitoring devices.
¢ The engineer will work closely with a geographically diverse design team to deliver state of the art ASICs for use in Emulex storage and networking products.
¢ BS CS/EE or MS CS/EE, and BSEE with a minimum of 6 years of relevant experience.
¢ Experience in state of the art stimulation tools, environment and methodologies.
¢ Excellent ability to analyze and solve problems related to ASIC development.
¢ Verilog, SystemVerilog, C, C++ and SystemC coding and experience in designing complete verification environments using VMM.
¢ Excellent communication skills with the ability to work in a team environment with multi-site product teams.
¢ Track record of ASICs taken from definition through production release.
¢ Ideally, a good understanding of network Storage, Fibre Channel (FC), NIC, iSCSI, TCP/IP, RDMA, ARM/Tensilica processors and interfaces such as PCI Express, SRIOV, 1/10/40/100 Gigabit Ethernet, AHB, APB, I2C, SM-bus, NCSI.
Mailto : firstname.lastname@example.org