- Architect and develop verification environment and testbench components such as BFMs and checkers.

- Verify design in block and chip level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification.

- Perform RTL code coverage, assertion coverage, and gate level simulations.

- Drive and adopt new verification methodologies and flows for efficiency improvements

- Mentor junior engineers on project execution

--Minimum 7 years or equivalent experience in ASIC design and verification

-- Experience in verifying designs at system level and block level

--SystemVerilog, VMM or UVM

-- System Verilog Assertions

-- Strong ASIC design verification flows and DV methodologies.

-- Strong and independent design debugging capability is a must

-- M.S. in Electrical Engineering, Computer Science, or Computer Engineering

Please Contact me for further details confidentially on this opening and other openings. 

We are here to assist you in your search please, call to discuss how we may present the best opportunity for your consideration and career growth. 

Thank You, 
Andrew Sanger 

Tara Technical Solutions. (TTS) 
Work: 408-850-1157 
Email: andrew@tarajobs.com 
http://www.linkedin.com/in/taratechnical