Our client northwest of Boston has an opening for a Lead ASIC/FPGA Engineer who is looking for the next step in their career as an ASIC Manager.

Must have prior leadership or project management experience, leading either chip design or verification.
Must have prior experience working with ASICs from spec to tapeout.
Must have experience with Verilog and some of the following: C/C++, scripting, Vera or SystemC
Any experience in the networking domain is a plus.

All qualified candidates are encouraged to contact me directly with any questions and/or your resume jspencer@connectedsp. com
Your resume will never be sent anywhere without your prior approval!