Job Description This position is for DV of a very high end state of the art SOC with integrated CPU

* Contribute to the development of overall DV strategy, environment build, test

development and coverage methodology

* Develop BFM's for the various modules of complex interfaces like PCIE/USB etc

* Create block and chip level test plans to verify proper functionality

* Create and Analyze coverage metrics to ensure completeness

Job Requirements * BS or MS in Electrical or Computer Science

* 5+ years verification , preferably in ethernet switch products or processor based SOC’s

* Good understanding of PCIE/Ethernet related protocols

* Developed Behavioral level models using Verilog/System Verilog

* Good programming skills in System Verilog and shell scripts

* Knowledge of SYSTEMC, TCL , PERL, a definite plus

* Contribute to creation of test plans at block/chip/system level, develop tests and run simulations

City/Town Bangalore

For more information mail to: jabeena.m@alpconsulting.in