I am working on some ASIC Verification Engineer positions for an IPO-Bound consumer products company for user interface devices. If you know someone who is actively looking for such a role, please send me their updated MS Word resume and we can get started right away: We have a very generous referral program and would like to reward you for your efforts. I look forward to hearing from you!

Here is a bit about the company:

-Private company in the midst of going public

-Leading edge technology with cutting edge applications such as gaming, handsets, and navigation.

-Significant revenue growth

Job Description:

- Knowledge and prior application of at least one of the following is a must : AVM, OVM, UVM, VMM, Specman

- Knowledge and prior application of pseudo-random verification methodology is a must : pseudo-random and functional coverage.

- Responsible for verification of assigned sections of a next generation technology.

- Development of architectural or other relevant reference models, test plans, test environments and suites

- Drive the process of RTL debug to ensure both functional correctness and adherence to key performance metrics

- Participate in post silicon validation planning and execution

- Contribute to development of advanced methods for architectural analysis and verification

- Domain knowledge is a must : telecom or networking background such as Ethernet, ATM, Sonet etc. OTN would be ideal but unexpected.

- Knowledge and prior application of SystemVerilog for verification is a must.

-Proficient in building constrained-random verification environments using advanced verification methodologies such as UVM, OVM, VMM or eRM

-Skill in creating and analyzing coverage metrics including functional coverage, assertion coverage and code coverage metrics is essential

-Experience with defining and creating SVA or PSL assertions, and using formal checking tools

-The engineer must have a well developed ability to analyze specifications at the architecture and micro-architecture level to identify the test scenarios needed to achieve functional and performance goals.

-Fluency with Verilog (preferably SystemVerilog) and C/C++/SystemC is required. TLM knowledge is a plus

-Hands-on experience with low power verification is desirable

-Good knowledge of scripting in Perl or other scripting language is necessary as well

-Bachelor’s in Engineering or equivalent required

-Knowledge and prior application of SystemVerilog for verification is a must.

Knowledge of SystemVerilog assertions is desirable.

-Knowledge of formal model checking using SystemVerilog assertions is desirable.

-At least 5 years experience as a verification engineer is a must.

-At least 2 years hands-on experience of AVM, OVM, UVM, VMM or Specman is a must.